How Chips Are Interconnected

How chips are interconnected

As Moore’s Law slows down, Chiplets and heterogenous integration offer a compelling way to continue improving performance, power, area, and cost (PPAC) . But choosing the best way to connect these devices so that they operate in a consistent and predictable manner is a challenge as the number of options continues to grow.

More possibilities also bring more potential connections. So while next-generation applications in AI, 5G, high-performance computing, mobile and wearables all benefit from various combinations of different devices in compact packages, it is challenging to just sort through the ever-increasing interconnect choices. But the bright side is that the industry is no longer bound by one set of rules, and the possibilities for customizing and optimizing systems are exploding.

Samsung, Intel, TSMC, and many other device manufacturers are focusing on optimizing die-to-die and die-to-package interconnects in various architectures, whether using microbumps , a vertical build that mixes bonding and bridging, or a horizontal build layer that uses fan-out redistribution. Deciding how and where to form interconnects is becoming an important part of system integration.

The roadmap for heterogeneous integration is moving towards more chip stacking through hybrid bonding, greater use of silicon bridges, silicon dioxide, and polymer interposers of increasing size. Architectures and packaging types are increasing to meet different end uses.

Table of Contents

Different architectures

“Advanced packaging architectures are expected to lead to exponential growth in I/O interconnection,” said Seung Wook Yoon, vice president of Samsung Electronics. Yoon gave a detailed introduction of the company’s advanced packaging FAB solution (APFS) for chip integration at IEDM, focusing on four key processes in the advanced packaging process – thin wafer dicing, hybrid bonding, thin wafer Lift-off (zero stress) and vertical interconnects . 

“For die technology, wafer thickness and bump pitch are key parameters. Currently, the most advanced HBM packages have a wafer thickness of less than 40 μm and stack more than 16 die into a single package.”

Samsung has four different package configurations: 2.5D RDL (R-Cube), 2.5D Silicon Interposer (I-Cube), 3D-IC stacking, X-Cube micro-bumps with hybrid bonding, and hybrid interposer ( H-Cube).

Increasing number of interconnects in high-bandwidth memory and AI high-performance computing

Increasing electrical, mechanical and thermal issues are also driving the development of HI process solutions. For example, TSMC demonstrated how it can solve the noise problem in a system consisting of 4 SoCs and 8 HBMs on a 50 x 54 mm organic interposer on a 78 x 72mm substrate. In this design, the minimum bump pitch of the micro-bumps used for chip-to-chip connection is 35 μm. An organic interposer (50 x 54 mm or 3.3X mask size) contains approximately 53,000 redistribution layer lines.

TSMC has integrated a discrete decoupling capacitor on the C4 bump side of its interposer dielectric, very close to the SoC device to ensure fast rejection of power domain noise. This in turn enhances HBM’s signal integrity at high data rates.

Thermal issues, while not new to the semiconductor industry, will become more severe as more computing and power management equipment is placed close to each other. Greely pointed to combinations such as memory and power management ICs, which often must be isolated within a single package. “Power management is like an old-fashioned hand warmer, and memory doesn’t like to go above 85°C, let alone 100°C.”

Interposers, whether silicon-based or polymer-based films, facilitate interconnects and act as stress-relief buffers for stacks of heterogeneous chips. Stress management and minimization of chip shift are ongoing issues that fabs are beginning to address from architectural planning and process perspectives.

A heterogeneous system is itself a system or a subsystem. They need System Technology Co-Optimization (STCO), the theme of IEDM as it celebrates the 75th anniversary of the invention of the transistor and looks ahead to the next 75 years.

Hybrid bonding

Hybrid bonding is so called because it bonds copper-to-copper pads and dielectric-to-dielectric fields simultaneously, providing the ultimate vertical connect. Compared to copper micro-bumping, hybrid bonding reduces signal delay to near zero while increasing bump density by a factor of 1,000. The micro-bump pitch is currently above 35μm. For hybrid bonding, pitches less than 20 µm are being evaluated.

Hybrid bonding

Clean interfaces and precise alignment are key elements for a production-worthy hybrid bonding process. Both wafer-to-wafer (W2W) bonding and chip-to-wafer (C2W) bonding processes are available. W2W is more mature, but it requires the same size chip and has little flexibility. Die-to-wafer flow is more complex and susceptible to inaccuracies in die placement alignment.

One way to improve placement accuracy is to perform collective D2W bonding of multiple dies simultaneously. There are also a variety of debonding methods that focus on minimizing substrate stress, reducing cost and increasing yield.

For example, thermal methods are cheap, but introduce stress and produce low yields. Alvin Lee, deputy director of Brewer Science, said the chemical method can be performed at room temperature, but the throughput is still low. Laser lift-off offers faster throughput and low stress, but at high equipment cost.

Next-generation photonic lift-off uses high-intensity light to quickly lift the wafer off the glass, introducing little stress at a more modest tool cost, Lee noted. Collective D2W hybrid bonding is an enabling technology for fan-out packaging.

Intel revealed its R&D progress in hybrid bonding, expanding from 10μm pitch copper-copper bonding in 2021 to 3μm pitch bonding last month. Some of the new process modules specifically optimized for hybrid bonding include tuning the PECVD oxide deposition process to deposit thick (20μm) low-stress films, improving oxide CMP slurries for faster polishing, and creating high-aspect-ratio etch-and-fill processes for vias through the dielectric.

Intel revealed its R&D progress in hybrid bonding, expanding from 10μm pitch copper-copper bonding in 2021 to 3μm pitch bonding last month.

Interposing structure

The interposer itself is not a discrete component. It is the intermediate structure between the chip (or die) and the underlying laminated substrate. Although the industry often refers to silicon interposers, the material that makes up silicon interposers is the dielectric, silicon dioxide. Polymer-based interposers are much less expensive than silicon interposers, but they lack reliability in some applications.

TSMC explored the benefits of organic interposers in terms of electrical performance, warpage control, yield and reliability. “Transmission loss is a function of line length. For a fixed energy-per-bit power consumption design budget, the interconnect length needs to be shortened to achieve high bandwidth,” said Shin-Puu Jeng, director of TSMC’s Backend Technology Service Department.

Bridge building

Intel and TSMC have been using proprietary silicon bridge technology to interconnect high-bandwidth memory modules and CPU/GPU. ASE recently introduced a packaging platform with embedded bridges capable of connecting die-to-die with 0.8-micron line-and-space (FoCoS-B).

“Due to the inherent fan-out RDL process limitations, FOCoS-CF and FOCoS-CL (chip-first-chip-last) solutions have high layer counts (>6 layers) and fine line/space (L /S = 1μm/1μm) in fabrication, suitable for applications that require high-density die-to-die connections, high input/output counts, and high-speed signal transmission,” said ASE’s Cao. FOCoS-B provides multiple options for the integration of multiple bridge chips.

In one example, 8 silicon bridge chips are embedded in two identical fan-out RDL structures with 2 ASICs and 8 HBM2e modules. They are mounted using two identical fan-out modules assembled on a flip-chip BGA substrate in the MCM. The FO modules are all 47 x 31mm, and the package size is 78 x 70mm.


Cao explained that ASE engineers also typically compare insertion loss, warpage and reliability of 2.5D with chip-behind and chip-front FOCoS approaches. Both FOCoS approaches demonstrate superior electrical performance over 2.5D Si TSVs due to the elimination of the silicon interposer and reduced parasitic capacitance and crosstalk.

Package-level warpage, mainly caused by CTE (coefficient of thermal expansion) mismatch between die and substrate and fan-out modules, showed better warpage control, and all packages passed open/short and functional tests before assembly , and reliability stress test JEDEC conditions.

Thermal management

In the package, more than 90% of the heat is dissipated from the top of the chip through the package to a heat sink, usually an anodized aluminum based heat sink with vertical fins. A thermal interface material (TIM) with high thermal conductivity is placed between the chip and package to help transfer heat. Next-generation TIMs for CPUs include sheet metal alloys such as indium and tin, and silver-sintered tin, which conduct 60W/mK and 50W/mK, respectively.

Engineers and material suppliers continue to explore alternatives to TIMs. “Materials that used to be rare are becoming rarer,” said Nathan Whitchurch, senior mechanical engineer at Amkor Technology. “So with sintered silver, you end up with a very thermally conductive silver alloy matrix between the lid and the die. The other is a softer TIM – the indium based type of stuff.


Die in advanced packaging are electrically interconnected by solder, microbumps, RDL and hybrid bonding. All of these connections need to remain reliable for the lifetime of the module. As package types proliferate and new processes with lower stress emerge, engineers are finding that the flexibility offered by heterogeneous integration may be worth all the challenges.

“Semiconductors are just beginning their die and heterogeneous journey because device scaling is becoming so difficult and expensive, and PPAC is shrinking with each advanced node,” said Samsung’s Yoon. “Chip design standards will become more prevalent, and more predictable ways of putting these devices together will take over. But all of this will take years and require the collection of big data, collaboration among partners, and experimentation across the value chain to determine what works .”

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